With integrated circuits becoming smaller and faster, improvement of device driving current is becoming more important. Device current is closely related to gate length, gate capacitance, and carrier mobility. Shortening poly-gate length, increasing gate capacitance, and increasing carrier mobility can improve the device current performance. Gate length reduction is an on-going effort coming with the effort to shrink circuit size. Increasing gate capacitance has also been achieved by efforts such as reducing the gate dielectric thickness, increasing the gate dielectric constant, and the like. In order to further improve device current, enhancing carrier mobility has also been explored.
Among efforts made to enhance carrier mobility, forming a stressed channel is a known practice. Stress can enhance bulk electron and hole mobility. The performance of a MOS device can be enhanced through a stressed-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
When silicon is placed under stress, the in-plane, room temperature electron mobility is dramatically increased. One way to develop stress is by using a graded SiGe epitaxy layer as a substrate on which a layer of relaxed SiGe is formed. A layer of silicon is formed on the relaxed SiGe layer. MOS devices are then formed on the silicon layer, which has inherent stress. Since the lattice constant of SiGe is larger than that of Si, the Si film is under biaxial tension and thus the carriers exhibit stress-enhanced mobility.
Stress in a device may have components in three directions: parallel to the MOS device channel length, parallel to the device channel width, and perpendicular to the channel plane. The stresses parallel to the device channel length and width are called in-plane stresses. Research has revealed that a bi-axial, in-plane tensile stress field can improve NMOS performance, and a compressive stress parallel to the channel length direction can improve PMOS device performance.
Stress can also be applied by forming a stressed capping layer, such as a contact etch stop (CES) layer, on a MOS device. When a stressed capping layer is deposited, due to the lattice spacing mismatch between the capping layer and the underlying layer, an in-plane stress develops to match the lattice spacing.
In further explorations, a local mechanical stress control technology has been reported to improve device performance by utilizing a high tensile sub-atmospheric material to form shallow trench isolation regions. After a post anneal process, stress is applied to active regions by shallow trench isolation regions. However, the stress improvement using this method is limited. All shallow trench isolation regions on a chip behave similarly in the post anneal process, thus applying a same type of stress to active regions on the chip. However, NMOS and PMOS devices demand different types of stresses. Improvement of the device performance on either NMOS or PMOS devices means degradation of the others.
Although multiple methods are effective in applying stress to channel regions of MOS devices, new methods, particularly methods for improving performance of both NMOS and PMOS device, are still demanded.